1. Field of the Invention
The invention relates to clock and data recovery systems used in high-speed optical and electronic receivers and, more specifically, to slicing techniques for data recovery.
2. Description of the Related Art
High-speed (e.g., 2.5-3.125 Gb/s) serial links are commonly used in optical communication links or for chip-to-chip interconnects in high-speed systems. For example, synchronous optical network (SONET) OC-192 links generate a 10-Gbps serial data stream on the optical links as well as its electrical representation just prior to the laser of the transmitter and after the optical detector of the receiver. At these speeds, optical dispersion phenomena (e.g., chromatic or polarization mode dispersion), electrical dispersion due to the frequency attenuation characteristics of the electrical interconnect, clock jitter, interference, and optical and electrical noise tend to corrupt the signals being transmitted, making their recovery difficult.
Typically, receivers in such systems attempt to slice a serial data signal at the center of symbol intervals since this is where the data integrity (i.e., signal-to-noise ratio) is generally best and the setup and hold times of the data signal to the slicer elements will be maximized. For example, in a 10-Gbps system, the symbol intervals are roughly 100 ps and the center slicing point would be roughly 50 ps from either the prior or subsequent anticipated symbol transition points for a given bit of the serial data signal. A slicer (i.e., effectively a one-bit analog-to-digital converter (ADC)) determines whether the sampled data is above or below a given threshold voltage. The threshold voltage is generally set midway between the voltage representing a logic “0” and the voltage representing a logic “1” for a given logic family (e.g., TTL or ECL). However, as will be discussed in the present invention, certain advantages can be drawn from placing thresholds at locations other than the mid point between the logical 1 and 0 values.
Alternatively, multiple distinct slicers can be utilized to sample the data signal at the center of symbol intervals. For example, two additional slicers can be employed with their respective thresholds set at, for example, roughly 25% and 75% of the range between voltages representing a logic “0” and a logic “1” for the system. Other slicer thresholds are also possible as well as different numbers of slicers. Alternatively, instead of multiple slicers (i.e., single-bit ADCs), a higher-order ADC of two or more bits can be used to sample data streams. As the number of bits in the ADC, or equivalently the number of slicers, increases, there is generally an increased system price to be paid in terms of chip area, power consumption, and/or temporal sampling accuracy. As a result, such samplers are generally undesirable in high-speed data recovery systems and one must resort to the absolute minimum number of slicers to achieve reliable detection.
Another technique to improve performance of data recovery in high-speed systems is oversampling. In an oversampling system, more than one sample per symbol interval is taken. Such samplers may take two, three, or more samples per symbol interval to improve the confidence level of each sample. By oversampling the input signal and then digitally processing the resulting digital samples, errant samples due to noise can be rejected, and improved recovery can be accomplished. However, straight oversampling comes at the cost of increased power consumption.